HAHAHAHA(HAx4)'s       




 RIP - Eastern Star 6/08/2015


And they have got the talent to make a happy ending out of everything.

zhouhu cache

And a metaphor here

    Posted by HAx4 at 2:07 PM 0 Comments  

 Sponsored by PulseRain Technology 3/07/2015


New Logo Test

    Posted by HAx4 at 2:07 AM 0 Comments  

 Notepad++ Je suis Charlie edition 1/21/2015

Freedom of expression is like the air we breathe, we don't feel it, until people take it away from us.

For this reason, Je suis Charlie, not because I endorse everything they published, but because I cherish the right to speak out freely without risk even when it offends others.
And no, you cannot just take someone's life for whatever he/she expressed.

Hence this "Je suis Charlie" edition.
- #JeSuisCharlie


============================
Notepad++ upgrade log, 01/21/2015

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    Posted by HAx4 at 10:06 PM 0 Comments  

 Errata for Quartus II 13.1 with System Verilog 1/12/2015

EDA softwares are expensive. That is probably not news to anyone who makes a living with them. Having said that, FPGA vendors usually offer a low cost version of synthesizer to their users. (To be fair, thousands of dollars is truly low cost in the EDA world.). And here is an errata I made in a hard way for one of them : Quartus II 13.1, web edition (Yes, that is free. I can't even afford thousands of dollars. :-(

Language : System Verilog

*) For the first always statement that appears in your code, please make sure it has reset_n in its sensitivity list

*) For true dual port memory, try set the data width no more than 16 bits. If you have to use 32 bits, use two of them in parallel, or use simple dual port memory (one port for read only, one port for write only.)

*) Pay attention to packed signed array, as described in the following:

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    Posted by HAx4 at 1:03 AM 0 Comments  

 Umbrella Revolution 10/01/2014

                                       “Birds born in a cage think flying is an illness.”                                                                            -- Alejandro Jodorowsky




Lyrics in Cantonese

    Posted by HAx4 at 6:14 PM 0 Comments  

 AES 9/09/2014

AES is a popular encryption algorithm with symmetric keys. If you are looking for open source AES implementions, Ref [1] is one of them.

To verify the AES implementation is in line with National Standard, use the test vectors from Ref[2] as passing criteria.

BTW,  China has its own flavor of encryption product regulation (Ref[3][4][5][6][7][8]). Ask Office of Security Commercial Code Administration (OSCCA) before the police knocking on your door. I'm not kidding, and HP knows it all well :-( (Ref[3]).


References:
[1] Ilya Levin, a byte-oriented aes-256 implementation
[2] Morris Dworkin, Recommendation for Block Cipher Modes of Operation, Methods and Techniques, NIST, 2001
[3] Xia Yu and Matthew Murphy, The Regulation of Encryption Products in China, MMLC Group
[4] CHINA’S EXPORT CONTROLS AND ENCRYPTION REGULATIONS
[5] 商用密码产品使用管理规定
[6] 境外组织和个人在华使用密码产品管理办法
[7] Mr.王掌柜, 中国有趣的“商用密码管理”
[8] 个人使用密码产品,例如 OpenSSL,是否属于违法行为?

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    Posted by HAx4 at 8:20 PM 0 Comments  

 Lab Notes - Regression Sim on Modelsim 8/26/2014

During regression simulation, more often than not you find yourself in a situation where you need to run a long list of test cases. And here is something that might be useful:

*) For the same .do or .tcl file, use "source xxx.do" will run it in batch mode, while use "do xxx.do" will run it in command line mode. The difference in those two modes is how the break is treated. For "source xxx.do", you can view it as run with "onbreak {resume}". i.e, if you use $stop in your code, you current simulation will resume and continue on, and the command that follows the "vsim xxx: will be executed.  While for "do xxx.do", the action after $stop will depend on the onbreak setting. You can set "onbreak {pause}" to pause the simulation and let you check the wave, or you can use onbreak{resume}, which will execute the next command that follows "vsim xxx" in the do file.

*) For regress test, you would kind like to let the simulation move on to the next case if everything works out, otherwise you might prefer to pause the simulation at the point where it fails. However, just by setting onbreak {pause} is not enough under this circumstance. If you simply calling $stop for the passing case, the simulation will still pause and balk the simulation flow. There are multiple ways to quit the simulation gracefully. One way to exit the current simulation gracefully is to shut off the clock and all other active signals, so the Modelsim will quit naturally due to the lack of active events (Ref [1][2])

However, I find it interesting to implement the clock-shut-off approach. For VHDL, you can set the clock as following:

clk <= ((not clk) and clk_en) after CLK_PERIOD / 2;

And you can use a process to set the clk_en to '0' to exit simulation successfully. But for system verilog, I initially tried something similar like

  always #(CLK_PERIOD/2) clk = (~clk) & (~test_all_done) ;

And the simulation didn't quit after test_all_done is raised. To make the magic happen, the clk can be implemented with a forever loop, like

initial begin
forever begin
#(CLK_PERIOD/2);

if (test_all_done) begin
break;
end else begin
clk = (~clk);
end
end
end

And you have to make sure all other initial statements will quit upon themselves after test_all_done is raised.


*) Ref[1] also showed some other tips that are worth noting for regression test simulation.

So the do file for your regression test might look like the following:

...
set total_num_of_cases 1000;list


for {set i 0} {$i < $total_num_of_cases} {incr i} {
    vsim xxxxxxx
    add log -r sim:/tb_xxx/*
    onbreak {pause}
    run -all
    quit -sim
    puts "Hi, Test case $i is done"
}
...

*) BTW, on a different note, Prof Harris rocks! (Ref[3])

References:
 [1] Modelsim Tips & Tricks

 [2] How to stop the simulation in VHDL TB

 [3] Fredric J. Harris, Multirate Signal Processing for Communication Systems, May 2004

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    Posted by HAx4 at 12:20 AM 0 Comments  

   

 

    

    
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