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Lab Notes - Altera LVDS Transmitter / Receiver
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5/11/2013
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If your FPGA device does not have hardcore SERDES, or if all you need is just a no-nonsense differential transceiver that could transfer data from one FPGA to another through a bunch of differential pairs, you might consider using the Megafunction in Ref[1].
To do that
(1) Make sure TX and RX FPGAs work from the same oscillator.
(2) Enable fast input/output registers
(3) Enable differential termination
(4) It is better to enable DPA at the receiver side, and wait until all the channels are locked on DPA
(5) After DPA is locked, the word boundary should be aligned. i.e, the bit-slip should be handled for each channel individually by toggling the rx_channel_data_align pin
(6) To handle bit-slip, the TX should be composed of into two states: alignment and normal. In alignment state, the TX should keep sending out a sync word, such as 0x5C until it gets an indication from RX that all channels are aligned. Such indication can be realized by using a GPIO from RX back to TX
(7) The receiver should keep doing the word-boundary-alignment until
(A) all channels are receiving the sync word correctly
(B) The sync word has been successfully received on all channels for a continuous number of cycles (set a threshold for this)
(8) After the alignment is finished, the receiver should notify the TX through something like a GPIO so that the TX can start its normal transmission.
(9) For megafunction setting, both TX and RX can be set with 180 degree phase offset between data and clock
(10) At the receiver side, the data is received on the clock out of LVDS_RX megafunction. You can use a FIFO to transfer the data to another clock domain. And start reading the data from FIFO when the FIFO is half full
References:
[1] LVDS SERDES Transmitter / Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide Ver 12.0, Altera Corp, Oct 2012
Labels: Embedded Systems, FPGA-ASIC-HW, Tech
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Lab Notes - SDC file for Quartus II
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5/08/2013
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(1) You can use create_generated_clock to create clock manually, or you can let the tool do that for you by using "derive_pll_clocks -create_base_clocks". The down side of the latter is that the clock name becomes a long string like {x_pll|pll_y_inst|altera_pll_i|general[0].gpll~.....}. But you can use set clk_name "...." to rename it.
(2) For source synchronous clock, start with "AN 433: Constraining and Analyzing Source-Synchronous Interfaces"
(3) For output delay, you could also use "-reference_pin" in set_output_delay statement (Ref[1])
(4) System Centric and FPGA centric
References:
[1] TimeQuest Example: Basic Source Synchronous Output
Labels: Embedded Systems, FPGA-ASIC-HW, Tech
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Lab Notes - Fs over 4
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4/30/2013
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I honestly think it is better to be a failure at something you love than to be a success at something you hate.
-- George Burns
IF signals can be expressed as
I * cos (2*pi * fc /fs * n) - Q * sin(2*pi*fc/fs*n) = real ((I+j*Q)*(exp(j*2*pi*fc/fs*n)))
If fs = fc * 4, the sample points become
I, (-Q), (-I), Q ...,
So the base band signal can be extracted in this case without any multiplication. However, the I and Q samples gathered in this method are offset with by 1/Fs in time.
You can live with such I/Q imbalance if the sample rate is high relative to symbol rate. Or you can do an interpolation/resampling to compensate for the 1/Fs offset.
References:
[1] Richard G. Lyons, Digital Signal Processing Tricks - Frequency Translation without multiplication, September 24, 2007Labels: Tech
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Don't give up on yourself!
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9/15/2012
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There’s nothing noble in being superior to your fellow men. True nobility is being superior to your former self.
– Hemingway
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Lab Notes - Access NTFS mount through cygwin
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8/13/2012
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The project I've joined recently has some restrictive rules for security reasons. One of them is to only store data on a specific network drive. In this case, it is a NTFS share. I have got authorization through my Windows Domain account, and everything works fine. However, when I start to access this NTFS share under Cygwin, I found that I can only get read access. And all the attempts to chown/chmod failed. And unfortunately, the IT guy was not immediately available at that moment. After spending half an hour trouble-shooting, I found that the Cywin mount has to be set like
mount -f -o noacl Z:/abc /home/hax4/abc
Thought it might be useful to write it down.
Labels: Linux, Software, Tech, Windows
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The Demise of ESD Magazine
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6/25/2012
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The future is a bit murky, at least to me, but the staff is busily getting all of the old issues online and are working on a revamped Embedded.com.
-- Jack Ganssle
Time has not been kind to the printing business. Finally, ESD, one of my two favorite magazines (The other is EDN) folded under the stampede of online content, leaving behind 11 years of good memory for me.
But if there is any silver lining, the last thing I got from reading its final issue is that C language is still the number one choice when it comes to embedded programming. As Dennis Ritchie (1941 – 2011) had put it in this way:
When I read commentary about suggestions for where C should go, I often think back and give thanks that it wasn't developed under the advice of a worldwide crowd.
So, Goodbye, ESD! And Good Luck, Embedded System Professionals!
In the past 10 years, I have seen so many ups and downs, and "forever" has never been in the vocabulary of this business. God, please tell me it's not the beginning of end for embedded system professions.
Labels: Embedded Systems, Limerick, Tech
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I'm a HAM, officially!
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5/26/2012
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It is only a technician class. But now I can put some good use in my Baofeng UV-3R+ :-)
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