Shift Registers have ample presence in things like FIR filters. Xilinx FPGA has built-in SRL16 primitive for this purpose. Close look at its pin layout reveals one peculiarity of this device (Ref[1]): It has no reset pin.

So it seems that the only way to initialize this device is to pump 16 zeros into it before taking any values out from its register chain. Lessons learned in the hard way show that the device would simply return zero for any of its registers when the initial data is not fully propagated through, even when none-zero data is actually present in part of its register chain.

Thus due consideration must be given during FPGA reset phase or at the end of FPGA configuration. A possible solution is to add a SRL16 init state into the Finite State Machine with a 4-bit counter in order to properly initialize SRL16.

References:
[1] 16-Bit Shift Register Look-Up-Table (LUT)

Posted by HAx4 at 8:30 PM

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